2022 roadmap on neuromorphic computing and engineering

Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 10$^{18}$ calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges for each research area. We hope that this roadmap will be a useful resource by providing a concise yet comprehensive introduction to readers outside this field, for those who are just entering the field, as well as providing future perspectives for those who are well established in the neuromorphic computing community

Etude de la technologie SOI partiellement désertée à très basse tension pour minimiser l'énergie dissipée et application à des opérateurs de calcul.

L'évolution des technologies des semi-conducteurs vers des géométries de plus en plus fines permet un accroissement des performances et des fonctionnalités par puce mais s'accompagne simultanément d'une augmentation de la puissance dissipée. Alors que les utilisateurs sont de plus en plus friands d'applications portables, la conception de circuits intégrés doit désormais prendre en compte le budget de puissance alloué. Il est donc essentiel de développer des circuits microélectroniques très basse puissance. La réduction de la tension d'alimentation VDD s'avère une approche très intéressante puisque cela permet de réduire la puissance dynamique quadratiquement et la puissance statique des courants de fuite exponentiellement. L'utilisation de tensions d'alimentation très basses (ULV) a été explorée à Stanford dès 1990 en utilisant une technologie spéciale, dont les transistors possèdent des tensions de seuil proches de zéro volt. Cependant, bien que réduire fortement la tension d'alimentation soit une méthode efficace pour diminuer la consommation, elle ne peut pas être appliquée arbitrairement car cela affecte négativement les performances, le délai dans les portes augmentant exponentiellement lorsque VDD devient inférieur à la tension de seuil. Il faut donc trouver un compromis entre vitesse et consommation. Du point de vue technologique, la technologie SOI-PD (Silicium sur Isolant Partiellement Désertée) s'avère très intéressante en ULV: elle présente des performances entre 25% et 30% supérieures à celles obtenues en CMOS à substrat massif. La technologique SOI permet donc de diminuer la consommation des circuits intégrés à fréquence de fonctionnement égale. Pour mieux appréhender le comportement des transistors SOI opérés en inversion faible, un modèle analytique et physique simple a tout d'abord été développé. La consommation d'un circuit dépendant fortement du style logique employé, plusieurs styles ont été comparés et celui présentant le meilleur produit puissance-délai a été choisi pour réaliser une bibliothèque de cellules standards. La problématique de la propagation de données sur des interconnexions longues, alors que les transistors fournissent peu de courant, a été abordée: un nouveau circuit de transmission en mode courant a été proposé. Enfin, un circuit de traitement d'image par paquets d'ondelettes a été développé et synthétisé grâce à la bibliothèque précédente

Etude de la technologie SOI partiellement désertée à très basse tension pour minimiser l'énergie dissipée et application à des opérateurs de calcul

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Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based Imagers

International audienceEvent-based imagers are bio-inspired sensors presenting intrinsic High Dynamic Range and High Acquisition Speed properties. However, noisy pixels and asynchronous readout result in poor energyefficiency and excessively large output data rates. In this work, we use Convolutional Spiking Neural Network filters to compensate these drawbacks and reduce output bandwidth by 10x. We designed a neuromorphic core as a distributable block that benefits from 3D integration technology with direct and parallel access to 32x32 pixels, enabling reduced frequency operation. Post-layout simulations depict a peak energy efficiency with 2.83pJ per Synaptic Operation (equivalent to 0.093fJ/event/pix) at the nominal literature input event rate

Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based Imagers

International audienceEvent-based imagers are bio-inspired sensors presenting intrinsic High Dynamic Range and High Acquisition Speed properties. However, noisy pixels and asynchronous readout result in poor energyefficiency and excessively large output data rates. In this work, we use Convolutional Spiking Neural Network filters to compensate these drawbacks and reduce output bandwidth by 10x. We designed a neuromorphic core as a distributable block that benefits from 3D integration technology with direct and parallel access to 32x32 pixels, enabling reduced frequency operation. Post-layout simulations depict a peak energy efficiency with 2.83pJ per Synaptic Operation (equivalent to 0.093fJ/event/pix) at the nominal literature input event rate

Performance Limits of Nanoelectromechanical Switches (NEMS)-Based Adiabatic Logic Circuits

This paper qualitatively explores the performance limits, i.e., energy vs. frequency, of adiabatic logic circuits based on nanoelectromechanical (NEM) switches. It is shown that the contact resistance and the electro-mechanical switching behavior of the NEM switches dictate the performance of such circuits. Simplified analytical expressions are derived based on a 1-dimensional reduced order model (ROM) of the switch; the results given by this simplified model are compared to classical CMOS-based, and sub-threshold CMOS-based adiabatic logic circuits. NEMS-based circuits and CMOS-based circuits show different optimum operating conditions, depending on the device parameters and circuit operating frequency

Backpropagation-Based Learning Techniques for Deep Spiking Neural Networks: A Survey

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Are SNNs really more energy-efficient than ANNs? An in-depth hardware-aware study

International audienceSpiking Neural Networks (SNNs) hold the promise of lower energy consumption in embedded hardware due to their spike-based computations compared to traditional Artificial Neural Networks (ANNs). The relative energy efficiency of this emerging technology compared to traditional digital hardware has not been fully explored. Many studies do not consider memory accesses, which account for an important fraction of the energy consumption, use naive ANN hardware implementations, or lack generality. In this paper, we compare the relative energy efficiency of classical digital implementations of ANNs with novel event-based SNN implementations based on variants of the Integrate and Fire (IF) model. We provide a theoretical upper bound on the relative energy efficiency of ANNs, by computing the maximum possible benefit from ANN data reuse and sparsity. We also use the Eyeriss ANN accelerator as a case study. We show that the simpler IF model is more energy-efficient than the Leaky IF and temporal continuous synapse models. Moreover, SNNs with the IF model can compete with efficient ANN implementations when there is a very high spike sparsity, i.e. between 0.15 and 1.38 spikes per synapse per inference, depending on the ANN implementation. Our analysis shows that hybrid ANN-SNN architectures, leveraging a SNN event-based approach in layers with high sparsity and ANN parallel processing for the others, are a promising new path for further energy savings

Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks

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